VLIW数字信号处理器64位可重构加法器的设计  

Design of VLIW Digital Signal Processor’s 64-bit Configurable Adder

作　　者：张志伟[1] 马鸿[1] 李立健[1] 王东琳[1] 

机构地区：[1]中国科学院自动化所国家专用集成电路设计工程技术研究中心,北京100080

出　　处：《计算机工程》2007年第16期29-31,34,共4页Computer Engineering

基　　金：国家自然科学基金资助项目(60473032)

摘　　要：描述了一款适用于超长指令字数字信号处理器的64位加法器的设计。该加法器高度可重构,可以支持2个64位数据的加法运算、4个32位数据的加法运算、8个16位数据的加法运算以及16个8位数据的加法运算。它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点,使得加法器的面积和连线减少了50%,而延时与加法器的长度的对数成正比。仿真结果表明,在典型工作条件下,采用0.18μm工艺库标准单元,其关键路径的延时为0.83ns,面积为0.149mm2,功耗仅为0.315mW。This paper presents the design of a highly re-configurable 64-bit adder, which is well suitable for VLIW digital signal processor. The adder can add two 64-bit operands, four 32-bit operands, eight 16-bit operands, or sixteen 8-bit operands. It is the hybrid of binary carry look-ahead adder of Brent-Kung~ and the carry select adder. By using this approach, the area and wiring of the adder is reduced by 50%, keeping the delay proportional to Olog n. Simulation results indicate that, typical conditions in standard cell using 0.18/am technology, the proposed adder can complete 64-bit addition in 0.83 ns and dissipates only 0.315roW with the area of 0.149mm^2.

关 键 词：可重构加法器 Brent-Kung树 进位选择 功耗延时积 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]