低功耗三值双边沿触发器设计  

Low power ternary double edge-triggered flip-flops

作　　者：杭国强[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310027

出　　处：《电路与系统学报》2007年第4期15-19,共5页Journal of Circuits and Systems

基　　金：国家自然科学基金资助项目(60273093);浙江省自然科学基金资助项目(Y106375)

摘　　要：提出了几种分别采用两个锁存器和单个锁存器的三值双边沿触发器设计方案,这些方案包括动态、半静态和静态结构。双锁存器三值双边沿触发器是通过将两个透明的三值闩锁并列构成的。单个锁存器的三值双边沿触发器设计是通过时钟信号的上升沿及下降沿后分别产生的窄脉冲使锁存器瞬时导通完成取样求值。三值双边沿触发器具有对时钟信号的两个跳变均敏感的特点,因此可以抑制时钟信号的冗余跳变。较之三值单边沿触发器,在保持相同数据吞吐量的条件下,采用三值双边沿触发器可使时钟信号的频率减半,从而降低系统功耗。最后给出了采用0.25μmCMOS工艺参数的HSPICE模拟结果及其功耗比较。Some CMOS ternary double edge-triggered flip-flops （TDETFFs） using one-latch and two-latch respectively, are presented. The proposed TDETFFs include dynamic, semi-static and static implementations. The two-latch TDETFFs are implemented by two transparent ternary latches in parallel. In the one-latch TDETFFs data are sampled into the latch during a short transparency period for each edge of the clock signal. In a TDETFF both rising and falling edges of the clock signal are used to transfer data from input to output. In this way, for a given throughput, the clock frequency can be halved with respect to a system using ternary single edged-triggered flip-flops （TSETFFs）, with a reduction of power dissipation. HSPICE simulations using 0.25μm CMOS technology demonstrate that the proposed flip-flops have a correct logic function and low-power characteristics.

关 键 词：多值逻辑 触发器 CMOS电路 低功耗设计 

分 类 号：TN432[电子电信—微电子学与固体电子学] TP333[自动化与计算机技术—计算机系统结构]