一种高精度动态CMOS比较器的设计与研制  

A precise dynamic CMOS comparator

作　　者：吴晓波[1] 吴蓉[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《电路与系统学报》2007年第4期119-123,118,共6页Journal of Circuits and Systems

基　　金：国家自然科学基金资助项目(90207001)

摘　　要：比较器的设计对于A/D、D/A转换器的精度至关重要。为满足14位高分辨率A/D转换器的需要,设计了一种高精度动态CMOS比较器,采用二级差分比较和一级动态正反馈latch结构实现了高比较精度。预增益和Latch级的应用降低了功耗。设计中充分考虑了工艺离散性和使用环境温度与电源变化的影响,保证了成品率和电路在变化工作环境下性能指标的实现。仿真结果表明,设计的高速动态比较器LSB(Least Significant Bit)为±0.15mV,输入动态范围为VSS^VDD(VSS为地电压,VDD为电源电压),相应于14位比较精度。功耗6.28mW,工作频率3.6MHz。电路用0.6μm双层金属、双层多晶硅CMOS工艺实现。The accuracy of A/D and D/A converters depends largely upon their inner comparators. To guarantee a 14-bit high resolution for an A/D converter, a precise dynamic CMOS comparator consisting of a two-stage differential cornparator together with a dynamic positive feedback latch is proposed. The improved circuit structure makes the comparator has a high gain as well as a high resolution. And the pre-gain and latch stages are introduced to lower power dissipation. Considering the parameter spread of devices in fabrication, corners models are adopted in simulation to ensure its yield and excellent performances in applications even when the power supply and environmental temperature is changed over quite a wide range. Simulation shows its LSB （Least Significant Bit） was ±0.015mV and the dynamic input range is VSS-VDD （VSS- is the level of the ground, and VDD is the supply voltage）, which means the resolution of 14-bit is achieved. And it also shows that the working frequency is up to 3.6MHz and the power consumption is 6.28mW. The circuit is realized in 0.6μm 2P2M CMOS process and the die area is about 400μm× 188μm.

关 键 词：比较器 正反馈 LATCH 

分 类 号：TN432[电子电信—微电子学与固体电子学]