高性能8位微控制器IP软核设计  

Design of 8-bit high-performance microcontroller IP softcore

作　　者：于冰[1] 沈健[1] 聂晶[1] 

机构地区：[1]合肥工业大学电气与自动化工程学院,安徽合肥230009

出　　处：《合肥工业大学学报（自然科学版）》2007年第8期1003-1006,共4页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(60373076)

摘　　要：在对传统MCS-51微控制器的局限性进行分析的基础上,提出了一种与其指令集兼容、性能大幅提高的可重用微控制器IP软核的设计。该控制器采用减少指令周期时钟数、独立总线访问、指令预读取等系统架构的优化及核心控制器架构的优化,使用新的加法和除法的算法,使性能得到大幅度的提高;在Altera FPGA上验证,该微控制器可稳定地工作在33.8 MHz时钟频率上。Based on the analysis of the limitation of the MCS-51 micro controller unit（MCU）, a high- performance reusable MCU IP softcore, which is compatible with MCS-51, is designed. In system architecture, the four-clock period per machine cycle architecture, the pre-fetching instruction method and the independent bus method are adopted and new arithmetic is used for addition and division, thus improving the MCU＇s power efficiency. Altera FPGA verification and simulation show that the presented MCU can run at 33.8 MHz clock frequency steadily.

关 键 词：IP软核 微控制器 MCU 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]