低功耗AESS盒的ASIC设计与实现  

ASIC Design and Implementation of Low-Power AES S-Box

作　　者：曾永红[1] 邹雪城[1] 刘政林[1] 雷鑑铭[1] 

机构地区：[1]华中科技大学电子科学与技术系超大规模集成电路与系统研究中心,武汉430074

出　　处：《微电子学》2007年第4期610-614,共5页Microelectronics

基　　金：国家高技术研究发展计划资助项目(2006AA01Z226);华中科技大学基金重点资助项目(2006Z001B)

摘　　要：S盒是高级加密标准(AES)硬件实现的关键,消耗了AES电路的大部分功耗。提出了一种基于合成域的异步流水线结构,以降低整个S盒的功耗。在电路实现中,电平敏感锁存器被插入数据通道中,以屏蔽动态竞争的传播。一种新的异步握手单元H-element组成的锁存控制器用来控制锁存器的开启和关闭。该S盒电路是一款采用0.25μm CMOS工艺的ASIC,较之合成域S盒电路,版图仿真结果表明,该电路以适宜的面积代价实现了低功耗。该电路可应用在诸如智能卡、无线传感器网络(WSN)节点芯片的嵌入式AES加密引擎中。S-box is the key step of hardware implementation of Advanced Encryption Standard （AES） and it consurnes much of the total power for AES. A new architecture of asynchronous pipeline over composite field was proposed to reduce the total S-box power. In this implementation, level-sensitive latches were inserted in datapath to block the propagation of the dynamic hazards. The opens and closes of latches were controlled by the latch controller based on an asynchronous handshake element, H-element. The circuit was an ASIC based on 0. 25 μm CMOS process. Layout simulation shows that the S-box circuit consumes less power than composite field S-box, whilst there is moderate area penalty. The proposed S-box circuit can be embedded in AES cryptographic engine for such applications as smart cards and wireless sensors network node chips.

关 键 词：S盒 专用集成电路 高级加密标准 合成域 异步流水线 

分 类 号：TN43[电子电信—微电子学与固体电子学] TP309[自动化与计算机技术—计算机系统结构]