或-符合型通用逻辑门组合电路的故障检测  

Faults detection in combinational circuits of OR-Coincidence type universal logic gates

作　　者：潘张鑫[1] 陈偕雄[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310028

出　　处：《浙江大学学报（工学版）》2007年第8期1260-1264,共5页Journal of Zhejiang University：Engineering Science

摘　　要：针对或-符合型三变量通用逻辑门组合电路,提出了一种基于布尔差分的故障检测方法.引入了或-符合代数中的布尔差分定义和运算性质,给出了在该组合电路中计算布尔差分的链式算法以及故障压缩定理.在此基础上,得到了电路单固定故障及双固定故障的检测方法.结果表明,在或-符合代数中布尔差分的计算较为简便,链式算法能有效地求得电路输出对全部原始及内部输入线的布尔差分,从而使得用布尔差分法对该组合电路进行故障检测具有简单、直捷的特点.并且用或-符合型三变量通用逻辑门实现函数连线数相对较少,因此在数字设计中使用这种逻辑门有利于故障检测.A method based on Boolean difference was proposed to detect faults in combinational circuits of OR-Coincidence type three-variable universal logic gates.The definition and calculation of Boolean difference in OR-Coincidence algebra were introduced to give chain-like algorithm for computing Boolean difference and faults collapsing theorems in the circuits.Then the single or double stuck-at-fault detection method was achieved.Boolean difference calculation is simple in OR-Coincidence algebra and the chain-like algorithm can effectively calculate Boolean difference of the circuit＇s output to all primary and internal input lines,so the Boolean difference method is convenient to detect faults in this circuit.In addition,the functions connection lines realized by using OR-Coincidence type three-variable universal logic gates are comparatively fewer,so it is benefit to detect fault by using this logic gate in digital designs.

关 键 词：通用逻辑门 或-符合展开 布尔差分 故障检测 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]