访存带宽最小化的H.264整像素运动估计VLSI结构  

VLSI architecture for H.264 integer-pel motion estimation with minimum memory bandwidth requirement

作　　者：李东晓[1] 郑伟[1] 张明[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2007年第8期1341-1347,共7页Journal of Zhejiang University：Engineering Science

基　　金：浙江省自然科学基金资助项目(Y106574);国家自然科学基金资助项目(90307002)

摘　　要：面向H.264/AVC整像素运动估计,提出了一种兼顾数据搬运和计算部件效率的全搜索超大规模集成电路(VLSI)结构.通过在片上最大化重用参考像素,使外存访问带宽得到了最小化,每个参考像素只需访存一次.通过分布式内存映射和图像边界的假想连接,使参考像素的搬运过程规则、高效.处理器单元(PE)结构简单,PE阵列以单指令多数据流(SIMD)方式工作,数据通信采用脉动方式,计算部件的利用效率为100%.搜索过程没有空泡,每拍处理一个搜索点,支持7种可变尺寸分块,同时完成41个分块的绝对差之和(SAD)的计算与比较.给出了参数化的结构设计描述.针对标准清晰度数字电视(SDTV)应用,设计实现了一个具体的结构,采用Faraday0.18μm CMOS标准单元工艺库,逻辑门数为151×103门,关键路径时延为3.86 ns,片上缓存为23.75 kB,访存I/O引脚数为8 bit.在216 MHz钟频下,实时支持SDTV 720×576@30fps,搜索范围为[-32,32]×[-16,16],2个参考图像,访存带宽为24.9 MB/s.A novel memory-access and computation efficient full-search verylarge-scale integrated-circuit（VLSI） architecture for H.264/AVC integer-pel motion estimation was proposed.With the highest level of on-chip data reuse,one-access for off-chip reference pixels was achieved,and the memory bandwidth requirement was minimized.By distributed data caching and imaginary connection of picture boundaries,the memory access of reference pixels was regular and efficient.Simple processing elements were systolically connected,and worked in single-instruction multiple-data（SIMD） manner,with 100% utilization.The proposed architecture fully supports variable block-size matching of H.264/AVC,and can produce 41 sums of absolute difference（SAD） for one search point every cycle without bubble.The architecture was described in parameterized design.For standard definition digital television（SDTV） applications,an implementation was accomplished based on the Faraday 0.18 μm CMOS standard cell technology,with 151×10^3 logic gates,3.86 ns critical path delay,23.75 kB on-chip memory,and 8 bit data I/O pins.Working at 216 MHz clock frequency,the implementation could support realtime SDTV 720×576@30fps,with the search range of [-32,32]×[-16,16],2 reference pictures,and 24.9 MB/s off-chip memory bandwidth.

关 键 词：H.264/AVC 运动估计 VLSI结构 数据重用 访存带宽 

分 类 号：TN919.81[电子电信—通信与信息系统]