0.18μm 12 GHz CMOS八分频电路设计  

Design of a 0.18 μm 12 GHz CMOS 1:8 Frequency Divider

作　　者：赵旭昊[1] 安凌凌[1] 孟令琴[1] 

机构地区：[1]南京电子技术研究所,南京210013

出　　处：《现代雷达》2007年第8期109-111,共3页Modern Radar

摘　　要：提出了一种基于高速锁存器的CMOS高速分频器结构,阐述了其工作速度,工作范围,前后级级联电路设计。采用典型的TSMC 0.18μm/1.8 V工艺模型,通过Agilent的ADS进行模拟验证,得到其最高工作速度为12 GHz,工作范围为3～12 GHz,在6～12 GHz内,输入灵敏度不小于100 mV,功耗小于28 mW。Based on a high speed latcher, a structure of CMOS high speed frequency divider is presented, and its operating speed ,operating range, requirement of different stages are described. Based on standard TSMC 0. 18 μm/1.8 V CMOS process model, the device is simulated with agilent software -ADS. Simulation shows that the circuit has a maximum work speed of 12 GHz, and it can work from 3 GHz to 12 GHz. The circuit＇s operating frequency is 6 GHz to 12 GHz under input signal amplitude of 〈 100 mV, and its power dissipation is less than 28 mW.

关 键 词：CMOS分频器 触发器 源级耦合逻辑电路 动态电阻 

分 类 号：TN772[电子电信—电路与系统]