90nm工艺SOC芯片多阈值低静态功耗设计  

Low Static Power SOC Design Based on Multi-Vt in 90 nm Technology

作　　者：易兴勇[1] 李海军[1] 陈杰[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2007年第9期812-815,共4页Semiconductor Technology

基　　金：国家自然科学基金资助项目(60425413)

摘　　要：为了降低纳米级芯片设计中功耗主体之一的静态功耗,从产生静态功耗的来源出发,提出了使用多阈值技术降低静态功耗,给出利用多阈值技术的多种实现方法。以COSTAR II芯片为实例,利用90 nm多阈值单元库进行低静态功耗设计。结果表明,利用多阈值技术设计来降低功耗是可行的,并对各种实现方法进行比较分析,可作为低静态功耗设计的参考。For the reduction of static power in chip design with nanometer process, which has become one of the primary components of power, the research work was mainly focused on sources of static power, proposes using muhi-Vt library technology to reduce power and provides several methods to implement it. A COSTAR II low-power design example with 90 nm muhi-Vt library was presented, and the results indicate that it is practical to reduce power by using muhi-Vt library. Besides, these implementation methods are compared and analyzed, which could provide a reference for low static power designs.

关 键 词：90 nm工艺 多阈值 低静态功耗设计 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]