CMOS图像传感器中数字噪声抑制技术研究  

Research of Digital Noise Reduction Technique in CMOS Image Sensor

作　　者：刘洪文[1] 张生才[1] 姚素英[1] 徐江涛[1] 

机构地区：[1]天津大学电子信息工程学院ASIC设计中心,天津300072

出　　处：《光电子．激光》2007年第4期411-413,共3页Journal of Optoelectronics·Laser

基　　金：国家自然科学基金资助项目(60576025);天津市重点科技攻关资助项目(033183911)

摘　　要：设计了一种可以降低CMOS图像传感器(CIS)中数字噪声对模拟信号影响的时序。在时序控制电路中加入了门控时钟,使数字电路各模块可分时工作,在模拟电路采样阶段保持静止以抑制噪声。理论分析和测试结果表明,采样阶段噪声减小70%,其他时间噪声减小20%。A timing circuit is designed to reduce the effect of digital noise on analog signal in CMOS image sensor（CIS）. Each module of the digital drcuits can work timesharing by adding gated-clocks ware and it can keep quiet to suppress onise when analog circuits are sampling. Theory analysis and experimental results show that the noise at sampling is reduced by 70% ,and 20% in other time. The method to keep digital circuit quiet when analog circuits are sampling can be extended to all high-precision mixed-signal integrated circuits design.

关 键 词：CMOS图像传感器(CIS) 数字噪声 时序 静止期采样 

分 类 号：TN386.1[电子电信—物理电子学]