嵌入式局部放电检测系统的数字滤波器设计  

Design of Digital Filter Used in Embedded Measuring System of PD

作　　者：郭亮[1] 黄宏新[2] 成永红[1] 陈小林[1] 孟永鹏[1] 

机构地区：[1]西安交通大学电力设备电气绝缘国家重点实验室,西安710049 [2]杭州市电力局,杭州310009

出　　处：《高电压技术》2007年第8期44-47,51,共5页High Voltage Engineering

基　　金：教育部博士点基金(20060698003)。~~

摘　　要：为较好地抑制来自电源的干扰和连续周期性干扰,提高系统的稳定性和抗干扰性能,介绍了在基于FP-GA的嵌入式局部放电信号检测系统中,对周期性正弦干扰进行抑制的新方法。根据FIR数字滤波器的原理,利用Simulink和DSP Builder构建了FIR滤波器的仿真计算模型,利用Matlab数字滤波器设计工具得到模型参数,对混叠高、低频干扰信号以后的放电信号进行滤波,达到预定的滤波效果后再将模型转化成能应用在嵌入式系统中的硬件描述语言。仿真结果验证了基于Simulink和DSP Builder设计硬件数字滤波器方法的可行性。和传统的设计方法相比,本文所给出的设计方法简化了开发流程、缩短了开发周期。In the embedded measuring system for partial discharge （PD） signals based on FPGA, a new method was introduced to suppress the periodical noises. According to the principle of FIR digital filter, models for simulating and calculating were developed with the toolboxes of Simulink and DSP Builder in the Matlab software. The coefficients of filter can be calculated according to the users＇ configuration. In order to simulate the PD signals with noises in the field detection, PD occurred in a single void was simulated and then mixed with noises of high and low fre- quencies. The PD signals with noises were introduced in the filter＇s model. Then, the model was converted into RTL codes in the form of VHDL or Verilog HDL which could be used in the embedded system. This design method is proved to be feasible in the process of design, conversion, and verification. Comparing with the conventional methods to encode one and more adders or multiplicators with low-level language, this method can simplify the developing steps, reduce the difficulty and shorten developing period. More importantly, models built with this method can be easily configured and modified, and RTL codes created by dsp Builder also have better performance. This design shows a good usage of the modern digital processing technology in the electrical engineering, especially in the PD measurement.

关 键 词：局部放电 在线监测 嵌入式 数字滤波器 FIR DSPBUILDER 

分 类 号：TM835[电气工程—高电压与绝缘技术] TN713.7[电子电信—电路与系统]