面向片上系统的高性能SDRAM控制器设计  

Design for High Performance SDRAM Controller Orienting to System on Chip

作　　者：张宇[1] 时龙兴[1] 王学香[1] 黄少珉[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,南京210096

出　　处：《固体电子学研究与进展》2007年第3期408-413,共6页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(批准号:60676011)

摘　　要：在分析了SDRAM存取原理之后,提出并设计了一种面向片上系统的高性能SDRAM控制器。该控制器采用数据写缓存方式降低了数据在存取内存时的等待时间;并引入了两组双通道预取指令缓冲器,每组双通道都用以减少取指令时的等待时间,采用两组的结构是为了增加指令预取的命中率;同时还使用了四路组关联的片上堆栈存储器来降低SDRAM的页失效频率,从而降低了因页失效而需要等待的时钟周期。实验证明,与传统的控制器相比,SDRAM的存取等待时间降低了63%,页失效频率降低了64%,总的指令执行平均时间为原来的40.5%。A high performance SDRAM controller orienting to system on chip is designed by analyzing the access of SDRAM. The controller uses the data write buffer to reduce the data access waiting time, and employs the two ways of duo channels instruction pre-fetch buffer to decrease the fetching instruction waiting time and increase the instruction pre-fetch buffer hit rate. Meanwhile, to reduce the waiting time aroused by page miss of SDRAM, a four ways of on chip stack memory is introduced. Compared with traditional controller through experiments, the novel SDRAM controller gets a high reduction up to 63% in access waiting time and 64% in page miss. And the procedure＇s running time on new controller is 40.5% as on the traditional controller on average.

关 键 词：片上系统 存储控制器 页失效 指令预取缓冲器 片上堆栈 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]