利用频域时钟抖动分析加快设计验证过程  

Accelerating Design Verification Process with Frequency Domain Clock Jitter Analysis

作　　者：Agilent Technologies Akihiko Oginuma 

机构地区：[1]安捷伦科技

出　　处：《电子质量》2007年第9期8-10,共3页Electronics Quality

摘　　要：随着数据速率的提高,时钟抖动分析的需求也在与日俱增。本文探讨参考了时钟的作用和时钟抖动对数据抖动的影响,并讨论在E5052B信号源分析仪(SSA)上运行的AgilentE5001A精确时钟抖动分析应用软件所配备的全新测量技术。Along with the improvement of data rate, the need for clock jitter analysis also is increasing day by day. The article discussed the clock function and clock jitter＇s influence to data jitter. Meanwhile, it also discussed the new measurement technology equipped in Agilent E5001A precision clock jitter analysis software which is run in E5052B signal source analyzer.

关 键 词：E5052B SSA 时钟抖动 

分 类 号：TP20[自动化与计算机技术—检测技术与自动化装置]