基于FPGA的数字传输抖动损伤的可控化实现方法  

Implementation of Controllable Jitter Impairment of Digital Transmission Based on FPGA

作　　者：俞彬[1] 罗明胜[1] 黄联芬[1] 姚彦[1] 

机构地区：[1]厦门大学通信工程系,福建厦门361005

出　　处：《厦门大学学报（自然科学版）》2007年第5期646-649,共4页Journal of Xiamen University：Natural Science

摘　　要：为了在室内模拟出一套可控的抖动损伤加载系统,省去数字传输网的各种设备室外调试耗费的大量的人力、时间和经费,本文首先简要分析了数字传输抖动产生的原因以及其对网络性能的影响.其次提出了利用正弦调制的方法进行抖动模拟,给出了双直接数字频率合成器(DDS)结构的实现方案.最后基于现场可编程逻辑阵列(FPGA)实现了中心频率、抖动频率和抖动峰-峰值均可控的抖动模拟算法.研究表明,采用双DDS结构实现抖动模拟方法切实可行,具有一定的使用价值.该算法已经在信道模拟器对数字传输的损伤加载模拟中得到应用,效果良好.The amount of human resource, time and expenses due to the outdoor debugging in the various devices of the digital transmission networks is very large. In order to develop a set of controllable indoor jitter-impairment-loadable system to reduce the a- mount,the reasons for the jitter generation in the digital communications and its impact on the performance of the networks were firstly analyzed in this paper, and then, a method of jitter simulation by sine modulation and a scheme of implementation with the structure of dual direct digital frequency synthesizer （DDS） were proposed, and finally, a simulation algorithm for the central frequency,frequency jitter and peak-to-peak value, all of which are controllable was implemented based on Field Programmable Gate Array （FPGA）. The results of the present work indicated that the structure with the dual DDS was feasible to simulate the frequency jitter and deserved actual application. This algorithm had been applied to simulation for the impairment of the digital communications in the channel simulator and obtained satisfactory results.

关 键 词：数字传输 抖动 现场可编程逻辑阵列 直接数字频率合成器 

分 类 号：TN915.11[电子电信—通信与信息系统]