FPGA测试中故障屏蔽现象的解决方法  

Masking of Faults in the Testing of FPGA

作　　者：李雪莲[1] 赵建新[2] 

机构地区：[1]山西大学,太原030006 [2]北方自动控制技术研究所,太原030006

出　　处：《电脑开发与应用》2007年第10期39-41,共3页Computer Development & Applications

摘　　要：以Xilinx公司FPGA的理论结构为结构模型,提出了FPGA测试中的故障屏蔽现象,并给出该现象的产生原因和判断条件,在此基础上进一步提出相应的解决办法和建议,避免或减少了故障屏蔽现象的出现,提高了测试FPGA的故障覆盖率。The Field Programmable Gate Arrays （FPGAs）are widely used in hardware implementation of many designed circuits. To detect the faults of FPGAs is very important, This paper discusses the problem which we called it the masking of faults. We focus on finding when and where it will appear, and give the methods and suggestions to avoid or reduce its appearing, thus the fault coverage is improved.

关 键 词：FPGA测试 测试方法 故障屏蔽 

分 类 号：TP391.76[自动化与计算机技术—计算机应用技术]