一种支持H.264和AVS的帧内预测器设计  

A Design of Intra Predictor Supporting H.264 and AVS

作　　者：徐张磊[1,2] 郑世宝[1,2] 杨宇红[1,2] 

机构地区：[1]上海交通大学电子工程系图像通信与信息处理研究所,上海200240 [2]上海交通大学上海市数字媒体处理与传输重点实验室,上海200240

出　　处：《中国图象图形学报》2007年第10期1735-1739,共5页Journal of Image and Graphics

摘　　要：为了使多标准视频解码器中的帧内预测器能够支持H.264和AVS两种视频标准,在对H.264和AVS两标准中的帧内预测计算模式进行分析,并对各模式计算公式之间相似性进行分析的基础之上,提出了一种支持H.264和AVS两种标准的,可配置的帧内预测值计算硬件架构。该架构由于将大部分预测模式的计算放到一个可配置的计算单元中进行,从而大大减少了芯片资源的浪费。为了提高处理速度,可采用4个相同的可配置的计算单元并行计算,一次计算出4个像素点的预测值。实验结果表明,该硬件架构在FPGA上占用10371个LUTs,频率可以达到150MHz。To adapt the intra predictor in multi-standard video coder to H. 264 and AVS stand, a configurable hardware architecture design of intra predictor that supports both H. 264 and AVS was proposed based on the similarities bebween the intra prediction algorithms in both standards. This kind of architecture can implement most intra prediction algorithms in one configurable calculate unit and thus can reduce the use of chip area. In order to enhance the speed of process, four parallel configurable generator unit are adopted in our design. This design was synthesized and the result showed that this architecture occupied 10 371 LUTs on FPGA and its frequency can be 150 MHz.

关 键 词：H.264 数字音视频编解码标准 帧内预测 硬件架构 可配置 

分 类 号：TN919.81[电子电信—通信与信息系统]