基于SoC的千兆EPON ONU硬件平台的设计与实现  

Design and implementation of Gigabit EPON ONU hardware platform based on SoC

作　　者：曹大为[1] 叶家骏[1] 张俊杰[1] 

机构地区：[1]上海大学通信与信息工程学院,上海200072

出　　处：《光通信技术》2007年第10期17-19,共3页Optical Communication Technology

基　　金：上海市科委集成电路专项(057062019)资助;上海市重点学科建设项目(T0102)资助

摘　　要：利用Altera Cycl oneTM II芯片完成了符合IEEE802.3ah标准的千兆EPON ONU硬件平台的设计和开发,并基于SoC在FPGA中嵌入8051处理内核以完善整个ONU系统的OAM功能。该硬件平台根据EPON ONU功能和逻辑代码的实现方式,具有性能稳定、配置维护灵活的特点。According to IEEE802.3ah standard, the design and implementation of gigabit ONU hardware platform is accomplished by using Altera Cyclone^TM Ⅱ FPGA, moreover, an 8051 core is embedded into FPGA to perfect OAM based on SoC. The hardware platform that is dependent on function of ONU, instruction of logical code and cost of ASIC manufacture, is provided with stable performance and flexible operation.

关 键 词：EPON ONU CYCLONE 2 SOC 硬件平台 

分 类 号：TN929.11[电子电信—通信与信息系统]