A Yield-Driven Gridless Router  

作　　者：周强 蔡懿慈 李舵 洪先龙 

机构地区：[1]Department of Computer Science and Technology Tsinghua University,Beijing 100084,China

出　　处：《Journal of Computer Science & Technology》2007年第5期653-660,共8页计算机科学技术学报（英文版）

基　　金：Supported by the National Natural Science Foundation of China(NSFC)under Grant No.60476014.

摘　　要：A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%.A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%.

关 键 词：design for yield critical area gridless routing integrated circuit layout 

分 类 号：TN915.05[电子电信—通信与信息系统]