多核、多线程处理器的低功耗设计技术研究  

Research of Low Power Design Techniques for Multi-core and Multithreading Microprocessor

作　　者：张骏[1] 樊晓桠[1] 刘松鹤[2] 

机构地区：[1]西北工业大学计算机学院,西安710072 [2]长安大学信息工程学院,西安710064

出　　处：《计算机科学》2007年第10期301-305,共5页Computer Science

基　　金：国家自然科学基金项目(60573107);国家自然科学基金项目(60573143)资助

摘　　要：随着微处理器设计技术和半导体制造工艺的进步,芯片的规模和复杂度急剧增大,超高的功耗密度时系统稳定性造成很大影响,功耗壁垒已经成为提升微处理器性能的最大障碍。本文介绍了低功耗设计的基本原理、研究内容、设计方法,分析了CMP和SMT体系结构的功耗需求和特性,讨论了不同的功耗优化策略在两种体系结构下的适用程度以及对性能造成的影响。针对多核、多线程体系结构,着重从系统级、结构级和电路级等不同抽象层次时典型的功耗优化技术做了讨论。最后,展望了未来微处理器低功耗设计技术的发展趋势。With the development of microprocessor design techniques and semiconductor fabrication, scale and complication of a single chip increase rapidly. The ultra high power density impacts the system stability seriously. Power wall is going to become the biggest obstruction for upgrading the performance of microprocessor. This paper presents the principle, content and techniques for low power design, analyses the power demand and characteristic of CMP and SMT architecture, and discusses the applicable degree and influence to performance when using different low power design techniques for these two architectures, and also discusses several typical power optimization techniques in different abstract level. At last, the development trend of the low power design of multi-core and multithreading microprocessor in the future is prospected.

关 键 词：多核 多线程 微处理器 低功耗 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]