RSA模乘器硬件优化设计  

Optimization Design of RSA Modular Multiplication Hardware

作　　者：吴东锋[1] 李华[1] 周瑛[1] 

机构地区：[1]重庆大学计算机学院,重庆400044

出　　处：《计算机科学》2007年第10期306-308,共3页Computer Science

摘　　要：在分析RSA算法的基础上,着重时核心的模来运算进行了优化,并在FPGA上时改进后的模来算法以及1024位的RSA密码算法进行了仿真。实验结果表明。优化效果较为理想。本文涉及RSA模乘器能够较好地满足现代电子政(商)务,变电站远程通讯等应用系统的实时性要求,具有良好的应用前景。Based on analysis about RSA algorithm, the paper focuses on the optimization of core modular multiplication operation and emulates improved modular multiplication algorithm and 1024-bit RSA cipher code algorithm in the FPGA platform. The experiment result indicates that optimization effect is relatively perfect. In the paper modular multiplication can satisfy modern electronic governmental affairs （electronic commerce） and remote communication of substation these application system＇s solid hour＇s need. It contains good application foreground.

关 键 词：RSA 模乘运算 MONTGOMERY 

分 类 号：TP393.08[自动化与计算机技术—计算机应用技术]