基于SRT算法的单精度浮点除法器  

A single-precision-floating divider based on SRT algorithm

作　　者：刘志刚[1] 汪旭东[1] 郑关东[2] 

机构地区：[1]河南理工大学电气工程与自动化学院,河南焦作454000 [2]暨南大学电子工程系,广东广州510632

出　　处：《电子技术应用》2007年第10期56-58,62,共4页Application of Electronic Technique

摘　　要：采用VHDL语言,在FPGA上实现了单精度浮点除法器的设计,通过采用SRT算法、SD表示法、常数比较法以及飞速转换法,进一步提高电路的运算速度。使用NC-sim和Maxplus2仿真软件进行前仿真和后仿真,使用Synplify进行逻辑综合,采用EPF10K40RC208-3芯片,对除法器进行了仿真。Using VHDL,a single-precision-floating divider is designed on a FPGA Chip,The operating speed is much further increased by using four methods-SRT algorithm,SD representation,Contant Comparison and Flying Transition.In the article,the presim and the post-sim based on EPF10K40RC208-3 is conducted by using the simulation software-NC-sim and Maxplus2,and the logic synthesis is conducted by using Synplify software.

关 键 词：除法器 SRT 单精度浮点 数字循环法 仿真 

分 类 号：TP332.22[自动化与计算机技术—计算机系统结构]