一种高速高精度采样/保持电路  

A High-Speed High-Resolution Sample-and-Hold Circuit

作　　者：杨斌[1] 殷秀梅[1] 杨华中[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《Journal of Semiconductors》2007年第10期1642-1646,共5页半导体学报（英文版）

基　　金：国家自然科学基金资助项目(批准号:90207001)~~

摘　　要：介绍了一种用于12bit,100MS/s流水线模数转换器前端的采样/保持电路的设计.该电路在3V电源电压100MHz采样频率时,输入直到奈奎斯特频率仍能够达到108dB的无杂散动态范围(SFDR)和77dB的信躁比(SNR).论文建立了考虑开关之后的采样保持电路的分析模型,并详细研究了电路中开关组合对电路性能的影响,同时发现了传统的栅源自举开关(bootstrapped switch)中存在的漏电现象并对其进行了改进,极大地减小了漏电并提高了电路的线性性能.A high performance CMOS sample and hold （S/H） circuit for use in the front end of a 12bit 100MS/s ADC is presented. It achieves a 108dB spurious-free dynamic range and 77dB signal-to-noise ratio over the Nyquist band at a 100MHz sampling frequency with a 3V power supply. An analysis model for the S/H circuit is built to capture the switching effect. The impact of the switches＇ arrangement is also addressed. The leakage in a conventional bootstrapped switch is analyzed and some improvements are made,enhancing the linearity significantly.

关 键 词：采样/保持电路 自举开关 增益自举放大器 

分 类 号：TN792[电子电信—电路与系统]