基于混合架构的H.264/AVC视频编码器设计  

Design of H.264/AVC Video Coder Based on Mixed Architecture

作　　者：张卫兵[1] 李先华[1] 石旭利[1] 滕国伟[1] 张兆扬[1] 

机构地区：[1]上海大学通信与信息工程学院新型显示技术及应用集成教育部重点实验室,上海200072

出　　处：《电视技术》2007年第10期30-32,共3页Video Engineering

基　　金：上海市科委攻关项目(055115008)

摘　　要：提出了基于DSP+FPGA混合平台的H.264/AVC编码器设计思路与实现方法。以DSP为主处理器,FPGA为协处理器实现算法的硬件加速,针对编码器中最复杂耗时的模块,设计相应的硬件加速引擎。并针对硬件加速引擎制定出便于控制和数据传输的软/硬件通信协议,实现了H.264/AVCD1编码器所需的实时性能。A design and implementation method of H.264/AVC encoder based on mixed structure is introduced, in which DSP is used as a main processor and FPGA as an assistant processor to accelerate arithmetic by hardware. In order to meet required real-time performance, hardware engine is designed for the most complicated and time-consuming module. According to the engine, it constitutes a software and hardware communication agreement, which makes control and data transporting easily, and realizes the real-time performances which H.264/AVC D1 coder needs.

关 键 词：运动估计 接口协议 混合架构 视频编码器 

分 类 号：TN919.81[电子电信—通信与信息系统]