一种向分支指令后插入冗余指令的容错微结构  

Injecting Redundant Instructions Behind Branches for a Fault-Tolerant Architecture

作　　者：张仕健[1] 胡伟武[2] 

机构地区：[1]中国科学院计算技术研究所计算机系统结构重点实验室,北京100080 [2]中国科学院研究生院,北京100039

出　　处：《计算机学报》2007年第10期1674-1680,共7页Chinese Journal of Computers

基　　金：国家"九七三"重点基础研究发展规划项目基金(2005CB321600);国家自然科学基金杰出青年基金项目"计算机系统结构研究"(60325205);国家自然科学基金(60603049);北京市自然科学基金(4072024)资助.~~

摘　　要：随着深亚微米工艺的广泛应用，瞬态故障已成为芯片失效的主要原因．文中提出了一种向分支指令后插入冗余指令的容错微结构，利用分支误预测浪费的处理带宽，降低了冗余执行导致的性能损失．实验结果表明，该技术的性能损失在6％～31％之间，平均为21％，明显低于MBI技术而和DIE技术的性能损失相当．该技术能够检测流水线上各阶段发生的瞬态故障并能恢复处理器状态，故障检测延时短，需要的硬件开销也较小，非常适合提高带有简单预测机制的嵌入式微处理器的容错能力．Since deep submicron manufacturing process is widely used m microprocessors, transient faults have become the main source of chip faults. A new fault-tolerant technique is proposed that inject redundant instructions behind primary branch instructions. It utilizes the wasted processing bandwidth during branch misprediction for redundant execution, hence the performance overhead is mitigated. The experiment results show that performance penalty resulted from the solution is ranging from 6 % to 31%, with an average of 21%, which is much lower than that of MBI technique and almost equal to that of DIE technique. The proposal can detect and recovery faults occurring in the entire pipeline, provides short fault detection latency and requires modest hardware cost. It is well suited to realize a fault-tolerant embedded microprocessor which has a simple branch predictor.

关 键 词：瞬态故障 时间冗余 容错 分支预测 嵌入式微处理器 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]