MD16:基于特定RISC规则的16位DSP处理器  

MD16:16-bit DSP processor with special RISC philosophy

作　　者：陈继承[1] 刘鹏[1] 姚庆栋[1] 史册[1] 郑德春[1] 余巧艳[1] 赖莉雅[1] 

机构地区：[1]浙江大学信息与电子工程学系

出　　处：《电路与系统学报》2007年第5期65-71,145,共8页Journal of Circuits and Systems

基　　金：国家高技术研究发展专项经费(2002AA1Z1140);霍英东教育基金(94031);浙江省重大科技项目(021101559)

摘　　要：为达到最佳的应用性价比,一个重要思想就是把RISC和DSP的优点融合在一个平台上,但是目前这方面工作侧重以RISC结构为基础构建RISC-DSP混合型处理器。与此对比,本文提出了一种以DSP为基础并辅以若干RISC特性的处理器构造思想。这种思想表现在体系结构设计上为采用局部类RISC同质寄存器结构来优化指令编码、采用基于二维扩展LAOD/STORE寻址机制来增强寻址能力;表现在微结构设计上为采用类RISC四级流水线来降低控制、数据相关性,同时由于基于寄存器的运算操作和扩展的LOAD/STORE寻址操作功能正交,因此又可采用指令内并行机制来提高运行效率。芯片采用SMIC 0.18μm6层CMOS工艺加工,在核心电压1.8V情况下,其可工作在0～162MHz,此时功耗为1.1mW/MHz。To achieve high performance/cost ratio, the idea of combining RISC and DSP functionalities into single architecture is a trend of booming and versatile embedded application system. Compared to the existed methods focusing on combining RISC and DSP functionalities with RISC bases, this paper puts up a novel idea of constructing DSP system with special RISC philosophy. Several methods are also brought up to realize this idea in detail. For DSP architecture design, local-homogenous register set is applied to optimize instruction encoding and two-dimensional extended LAOD/STORE mechanism is used to enhance the memory access capabilities. For microstructure design, four-stage RISC-like pipeline is adopted to decrease control and data dependencies. Owing to the orthogonality of register-oriented computation and extended LAOD/STORE, Inner ILP （instruction level parallel） becomes reasonable and is utilized to improve system efficiency. Under SMIC 0.18μm CMOS technology, the chip can run up to 162MHz with power consumption of 1.1mW/MHz.

关 键 词：DSP RISC 指令内并行 寄存器组 

分 类 号：TN402[电子电信—微电子学与固体电子学]