运用级间并联电感的级联CMOS低噪声放大器的优化设计  

Optimize cascade CMOS low noise amplifier using inter-stage inductor

作　　者：李霖[1] 楼东武[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310027

出　　处：《电路与系统学报》2007年第5期88-91,共4页Journal of Circuits and Systems

摘　　要：本文介绍了一种运用级间并联电感优化CMOS低噪声放大器的设计方法。传统的级联低噪声放大器可以从两级级联放大器的角度出发,视为共源级和共栅级的级联,由于共栅极的极好的隔离性,两级放大器可以分别设计。理论分析表明:在共源极和共栅极间引入级间匹配网络,即并联一个电感加强两极间的耦合,可以有效的改善低噪放的功率增益和噪声性能。文章最后用一个工作于5GHz的低噪放的设计实例,验证了理论分析的正确性。In this paper, a novel design method for RF CMOS low noise amplifiers （LNA） is presented, the cascade LNA is considered as a two-stage amplifier. Considering the high isolation property of the common gate stage, the two stages can be designed separately. A parallel inductor is used as the matching component, which increases the overall gain and decrease the noise figure. Using this method, a 5GHz LNA is designed and simulated to verify the validity of theoretical analysis.

关 键 词：低噪放 级联 级间电感 功率增益 噪声 

分 类 号：TN722.3[电子电信—电路与系统]