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机构地区:[1]浙江大学超大规模集成电路设计研究所,杭州310027
出 处:《微电子学》2007年第5期721-725,共5页Microelectronics
基 金:国家自然科学基金资助项目(90207001);浙江省自然科学基金资助项目(Z104441)
摘 要:提出了一种基于1.5μm BCD(Bipolar-CMOS-DMOS)工艺的低压低功耗高增益运算放大器。该放大器可在低至1.8 V的电源电压下正常工作。设计中采用多级差分级级联和共模反馈结构,通过双重嵌套式米勒补偿结构进行补偿。新颖的带有静态电流控制的甲乙类输出级使得在实现轨到轨输出的同时,有效地减小了放大器的交越失真。测试结果表明,提出的设计目标均已实现,放大器在5 V的电源电压下,开环增益达到96.3 dB,在10 V/V固定增益比应用时,增益误差为±0.06%,-3 dB带宽为45 kHz,静态工作电流在60μA以下。Based on 1. 5 /μm BCD technology, a low-voltage/low-power and high gain operational amplifier was proposed, which could operate at 1.8 V supply voltage. Multi-stage differential cascade structure and common-mode feedback loop were adopted. Stability of the circuit was greatly improved by using double nested Miller compensation technology. A quiescent current-controlled class AB output stage minimized quiescent current and decreased crossover distortion while rail-to-rail output swing was implemented. Test results showed that anticipated performances were achieved. The op-amp has an open loop DC gain of 96.3 dB at 5 V supply voltage, and in closed loop applications with 10 V/V gain, the circuit has a -3 dB bandwidth of 45 kHz, a gain error of ±0. 06% and a quiescent current less than 60/μA.
关 键 词:运算放大器 Rail-to-Rail输出 共模反馈 嵌套式米勒补偿
分 类 号:TN433[电子电信—微电子学与固体电子学]
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