总线可重配置的多处理器架构  

Multi-core System with Reconfigurable Datapath

作　　者：张磊[1] 徐国治[1] 应忍冬[1] 

机构地区：[1]上海交通大学电子工程系,上海200240

出　　处：《微计算机信息》2007年第32期5-7,共3页Control & Automation

摘　　要：本文提出了一种全新的总线可重配置的多处理器架构。该架构结合了多核与可重配置处理器的优势,具有并行性高、计算能力强、结构复杂度低并且应用领域广泛灵活的特点。对于该架构的实现,本文提出了VHDL层面的软件模拟。通过简化模型,用多个改进后的VHDL实现的8051核以及可重配置的多路开关进行了软件模拟。We put forward a new architecture： Multi-core System with reconfigurable datapath. This architecture combines the advantage of multi-core and reconfigurable processor, possesses characteristic of high parallelism,strong computing ability,low complexity and wide range of flexible application. For the realization of this architecture, we propose a software simulation by VHDL. In the VHDL level, we do software simulation by simplifying the model of architecture and utilizing many improved 8051 cores and reconfigurable multiplex switches.

关 键 词：可重配置处理器 多核 总线可重配置 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]