基于多核处理器的高性能IPSec软件架构的研究  

Research for High Performance IPSec Software Architecture on Multi-core Processors

作　　者：蒋汉平[1] 李腊元[1] 

机构地区：[1]武汉理工大学计算机科学及技术学院,武汉430063

出　　处：《武汉理工大学学报（交通科学与工程版）》2007年第5期792-795,共4页Journal of Wuhan University of Technology（Transportation Science & Engineering）

基　　金：国家自然科学基金项目(批准号:60672137);教育部高等学校博士点基金项目(批准号:20060497015);湖北省科技攻关项目(批准号:2007AA101C63)资助

摘　　要：随着网络的发展,高性能的安全应用在构建未来网络系统中发挥着越来越重要的作用;同时,基于网络处理器成功构建一个安全网络系统的关键,在于网络处理器软件系统的设计与开发,其核心问题就是要安全软件系统充分发挥网络处理器灵活性和高性能的特点.针对目前最为先进的OCTEON基于M IPS64的多核处理器,结合多核技术设计了高性能的IPSec软件架构并进行验证,给出了基于选定硬件平台上的IPSec的测试方案和性能数据.With the network development, high performance security application plays more important roles in the network systems. Network processors satisfy the demand for intelligent processing at wire speed and system flexibility. The paper presents the outline of design and challenges which a designer may face while designing high performance IPSec system using network processors. It introduces the hardware architecture of multi-core network processor and software framework of IPSec. The OCTEON is selected which is a fully capable microprocessor SOC implementing the MIPSv264-bit instruction set with security and packet processing instructions forming the cnMIPS core to verify the IPSec software architecture. At last, the IPSec performance data are given.

关 键 词：IPSEC 多核网络处理器 数据平面 快速通道 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]