高层次综合中面向功耗优化的方法与技术  

An Overview of Power Optimization in High Level Synthesis

作　　者：刘志鹏[1] 边计年[1] 周强[1] 

机构地区：[1]清华大学计算机科学与技术系,北京100084

出　　处：《计算机辅助设计与图形学学报》2007年第11期1373-1380,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(90407005);国家自然科学基金重点项目(90607001)

摘　　要：介绍了高层次综合阶段面向电路功耗的主要优化方法及其研究进展.集成电路设计制造工艺的持续发展使得电路功耗逐步超越了原有的面积、时延等指标,一举成为设计的主导因素.研究表明:集成电路设计层次越高,对电路功耗的优化潜力也就越大,这就要求设计人员在高层次综合阶段即开始考虑对功耗进行有效的降低和优化.对本领域具有代表性的算法进行了系统的描述,并且对这些算法的基本思路进行了相应的分析和总结.Power aware algorithms an this paper. With the rapid development delay or area to become the most importa design level will cause the power dissipation different potential in the described systematically, and high-level their basic d recent researches in high-level synthesis procedure are reported in of IC technology, power consumption of circuits has surpassed the nt design concern in IC design automation. It is noted that different for power saving, thereby it is necessary to optimize and minimize synthesis. In this paper, the typical algorithms in the field are principles are also analyzed and summarized.

关 键 词：高层次综合 低功耗 开关频度 热密度 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]