基于层次化总线的多处理器系统芯片设计与测试  

Design and Test of an Multi-Processor System-on-Chip Based on Hierarchy Bus

作　　者：杜高明[1] 章伟[1] 高明伦[1] 

机构地区：[1]合肥工业大学微电子设计研究所,安徽合肥230009

出　　处：《电子测量与仪器学报》2007年第5期105-108,共4页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金资助项目(编号:60576034;60373076);教育部博士点基金资助项目(编号:20050359003)

摘　　要：在单个芯片上集成多个处理器以提高SoC的整体性能已成为下一代集成电路设计趋势。如何提高其中多个处理器之间的通讯效率则成为MPSoC的设计关键。传统SoC平台中多以单总线结构为主,随着SoC中IP数目的增加,通讯效率随之降低。基于MPSoC环境下,提出一种层次化总线结构:本地总线负责处理器与本地内存通讯;全局总线实现对全局设备的访问。两级总线通过总线桥连接。在RTL级设计了上述平台,以流水矩阵乘法为例研究其在不同工作负载下的加速比变化。实验结果表明,在四个处理器的情形下,循环次数为4次时加速比仅为2.2;随着循环次数增多,加速比可达3.2。Integrating multiple processors into a single chip to enhance performance has become a trend in high performance System on Chip （SoC） design. And the major challenge is how to improve the efficiency of the communication architecture. Instead of choosing single layered bus used in traditional SoC, hierarchy bus based architecture was proposed in our MPSoC platform. Local traffic communicates through the local bus, and the global bus carries out the access to global devices through the second layer. The MPSoC platform was implemented in RTL and tested by a pipelined-matrix-multiplication program. The number of multiplication cycles was parameterized to generate different workloads. The experimental result shows that under the condition of 4 processors, when the number of multiplication cycles is 4 the speedup is only 2. 2, as the number of multiplication cycles increases the speedup can reach up to 3.2.

关 键 词：多处理器系统芯片 双层总线 加速比 

分 类 号：TN402[电子电信—微电子学与固体电子学]