VLSI版图DRC验证算法的优化  

A New Optimizational Algorithm for VLSI Layout Physical Verification

作　　者：郭雅琳[1] 陈岚[1] 

机构地区：[1]中国科学院计算技术研究所,北京100086

出　　处：《微电子学与计算机》2007年第11期186-188,共3页Microelectronics & Computer

摘　　要：介绍了版图验证的几种方法:扫描线算法和层次化验证算法,并比较其优缺点,最后着重介绍了层次式与扫描线综合验证算法,并在SUN工作站上用C++实现。The work introduced in this paper mainly investigates several algorithms of layout verification such as scanning line algorithms and hierarchical layout verification algorithms. At last, we synthesized these algorithms that mentioned above and applied it on SUN workstation by C＋＋.

关 键 词：版图验证 层次式算法 扫描线算法 VLSI 深亚微米DSM 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]