Quasi-Static Energy Recovery Logic with Single Power-Clock Supply  

准静态单相能量回收逻辑(英文)

作　　者：李舜[1] 周锋[1] 陈春鸿 陈华[1] 吴一品[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203 [2]温莎大学电子与计算机工程系

出　　处：《Journal of Semiconductors》2007年第11期1729-1734,共6页半导体学报（英文版）

基　　金：国家自然科学基金资助项目(批准号:90307008)~~

摘　　要：This paper presents a new quasi-static single-phase energy recovery logic （QSSERL）, which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control volta- ges. This not only ensures lower energy dissipation, but also simplifies the clock design, which would be otherwise more complicated due to the signal synchronization requirement. It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts. Simulation with an 8bit logarithmic look- ahead adder （LLA） using static CMOS,clocked CMOS adiabatic logic （CAL,an existing typical single-phase ener- gy recovery logic）,and QSSERL,under 128 randomly generated input vectors,shows that the power consumption of the QSSERL adder is only 45% of that of the conventional static CMOS counterpart at 10MHz, and the QS- SERL adder achieves better energy efficiency than CAL when the input frequency finput is larger than 2MHz.提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.

关 键 词：energy recovery adiabatic logic low power digital CMOS VLSI 

分 类 号：TN432[电子电信—微电子学与固体电子学]