一种高效的H.264去块效应滤波器VLSI结构设计  

An Efficient VLSI Architecture for H.264 Deblocking Filter

作　　者：席迎来[1] 王凤琴[1] 郝重阳[1] 周巍[1] 

机构地区：[1]西北工业大学电子信息学院,陕西西安710072

出　　处：《西北工业大学学报》2007年第5期716-721,共6页Journal of Northwestern Polytechnical University

摘　　要：最新的视频压缩编码标准H.264在编解码系统中引入了自适应的去块效应滤波器。去块效应滤波器可以有效地消除块边界的方块效应,但同时也带来了运算量的增加。文中针对H.264去块效应滤波器的硬件原型进行了设计,所设计结构可以大大降低硬件系统的处理周期。在所设计的结构中采用了以下4个关键技术:滤波边界顺序调整、存储单元分配、滤波器架构和双转置寄存器组来提高系统的并行处理能力。仿真结果表明,文中所提出的架构,仅需要288个时钟周期即可实现一个16×16宏块的滤波。滤波器模块只占用16.3 k逻辑门和640 byte的b lock RAM,具有很高的时间-面积效率。H. 264 adaptive deblocking filter adds considerably to the formidable amount of calculation time needed by the video coding standard H. 264. We now present a method that we believe can much reduce the calculation time needed by the filter. In the full paper, we explain our efficient method in some detail. In this abstract, we just add some pertinent remarks to listing the one topic of explanation, which is： the design of the VLSI architecture of the deblocking filter. Its four subtopics are： the reordering of border filtering （subtopic 1.1）, memory distribution （subtopic 1.2）, filter architecture （subtopic 1.3）, double transpose register array （subtopic 1.4）. In subtopic 1.1, we discuss fairly thoroughly how reordering can considerably reduce the calculation time needed by the filter. In subtopics 1.3 and 1.4, we also discuss fairly thoroughly how judicious changes in filter architecture can reduce the calculation time required by filter. Finally we present numerial simulation results, which are summarized in a table in the full paper. These results show preliminarily that only 288 clock cycles are needed to finish filtering a macroblock for proposed architecture, and the synthesized logic gate count is only 16.3 k and 64 byte block RAM.

关 键 词：H.264/AVC 去块效应滤波 VLSI 

分 类 号：TN91[电子电信—通信与信息系统]