VLSI设计中容性交叉耦合对时序分析的影响  

Studies on Timing Analysis for Coupling Interaction in VLSI Design

作　　者：刘晓晓 刘庆江[2] 马光胜[1] 冯刚[1] 

机构地区：[1]哈尔滨工程大学计算机科学与技术学院,黑龙江哈尔滨150001 [2]哈尔滨师范大学计算机科学系,黑龙江哈尔滨150001

出　　处：《小型微型计算机系统》2007年第11期2062-2065,共4页Journal of Chinese Computer Systems

基　　金：国家自然科学基金项目(60273081)资助.

摘　　要：互连线间的容性交叉耦合已成为影响线路延迟的一个重要因素,因此本文将阶层设计中有意义的层次结构考虑到电路时序分析中,在存在静态敏化和动态敏化交叉耦合的电路中提出了局部伪交叉耦合和全局伪交叉耦合的概念,给出了一种利用模块间功能关系考虑由于模块间连接而产生的全局伪交叉耦合的综合的时序分析方法.实验数据证明,本文方法在不影响运行速度的前提下可以有效地识别出伪交叉耦合,提高了时序验证的准确性.Capacitive coupling interaction between neighboring nets can contribute to a large portion of the delay of a line this paper considered the hierarchically meaningful structure to circuit delay analysis, injected the notions of local false coupling interaction and global false coupling interaction in both statically and dynamically sensitizable circuits, and then proposed acomprehensive approach to identify valid interaction using functional relations considering global false coupling interaction generated by connections between modules. Experiments on benchmark circuits show that this method can efficiently identify the global false coupling interaction without influencing running speed, then improves the accuracy of hierarchical timing verification.

关 键 词：时序验证 交叉耦合 耦合电容 层次设计 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]