一种新型数字高精度伪码快速捕获延迟锁定环的设计与实现  

Design and Implementation of a New Digital,High-Precision,Fast Pseudo-Code Capture and Delayed Locking Loop

作　　者：张树勇[1] 曹永刚[1] 郭岩[1] 

机构地区：[1]中国人民解放军驻沈阳飞机工业(集团)有限公司军事代表室,辽宁沈阳110034

出　　处：《飞机设计》2007年第5期76-80,共5页Aircraft Design

摘　　要：介绍了一种新型全并行快速捕获延迟锁定环的设计与FPGA实现,捕获时间小于等于一个伪码周期,抗干扰容限大于80 dB。此快速捕获延迟锁定环实现127路全并行捕获和高精度跟踪,仅需存储130个PN码表,相对于其他并行捕获延迟锁定环或串并结合的环路,存储量约小2/3,并具有较高捕获精度。This paper describes the design and FPGA implementation of a new full parallel, fast capturing and delayed locking loop. The capture time is less than or equal to one pseudo-code period and the anti-jamming tolerance is larger than 80 dB. The fast capture and delayed locking loop achieves full parallel capture and the high accuracy tracking in 127 loops, and it is required only to memorize 130 PN code lists （ that are approximately 1/3 of those for other parallel capture delayed locking loops or series-parallel loops）, and provides higher capture accuracies than other loops.

关 键 词：FPGA 伪码 捕获 跟踪 

分 类 号：V243[航空宇航科学与技术—飞行器设计]