H.264中二进制算术编码的硬件实现  

Hardware Realization of Binary Arithmetic Coding for H.264

作　　者：陈传东[1] 陈新[1] 

机构地区：[1]福州大学物理与信息工程学院,福建福州350002

出　　处：《现代电子技术》2007年第22期48-50,共3页Modern Electronics Technique

基　　金：福建省科技厅集成电路(IC)技术平台建设项目(2003Q013)

摘　　要：H.264标准中的二进制算术编码算法复杂,用软件实现起来速度慢,编码一个信号需要多个时钟周期。结合硬件实现特点,对算法流程进行合理优化,采用流水线设计方法,电路结构采用Verilog HDL进行RTL级描述,在Synplify平台上进行FPGA综合,介绍了H.264中二进制算术编码的FPGA实现方案。编码速度达到1 b/cycle,工作频率达到75.7 MHz,完全可以应用于视频图像的实时编码中。The binary arithmetic coding in H. 264 is complex and in a low speed realized by software, it needs much period of encoding a signal. By using pipeline design method, the working flow is optimized according to hardware realization. The architecture is described by Verilog HDL on the RTL level, and is synthesized and tested by FPGA. It can encode a binary symbol each cycle and can work at a speed of 75.7 MHz and can be used in the video compression system.

关 键 词：二进制算术编码 H.264 CABAC FPGA 

分 类 号：TN919.81[电子电信—通信与信息系统]