a-Si双栅TFT对电泳显示器响应速度的改善  

Dual-gate Amorphous Thin Film Transistors for Electrophoretic Display Response Speed Optimization

作　　者：杨澍[1] 荆海[1] 付国柱[1] 马凯[1] 

机构地区：[1]中国科学院长春光学精密机械与物理研究所北方液晶工程研究开发中心

出　　处：《液晶与显示》2007年第5期565-571,共7页Chinese Journal of Liquid Crystals and Displays

基　　金：国家"863"计划资助项目(No.2004AA303560)

摘　　要：第一次提出了共栅极双栅结构用于不定形硅薄膜晶体管(a-SiTFTs)的像素结构,通过控制高源漏电压下的过大漏电流,解决有源矩阵电泳显示器(AM-EPD)响应速度慢的问题。文章通过与单栅a-SiTFTs的对比分析,预期到采用等沟道长度双栅结构将在保持开态电流基本不变的情况下有效减小关态漏电流。SPICE模拟结果证明,双栅结构使关态漏电流减小一倍左右。为了衡量该结构对缩短电泳显示器响应时间的作用,建立了响应时间t与漏电流Ioff之间的函数关系。通过Matlab模拟,证明双栅结构在漏电流为20pA时可将响应时间从380ms降至320ms;漏电流为35pA时可将响应时间从530ms降至360ms,帧频由2Hz提高到3Hz。根据建立的t-Ioff关系,指出降低电泳粒子半径和增大存储电容是进一步提高电泳显示器响应速度的关键。Dual-gate structure with a common gate design is applied to amorphous silicon transistors （a-Si TFTs） for the first time, to solve the problem of slow response speed of electrophoretic display （EPD）, by regularizing the over-ranged drain-source leakage currents under high voltages. In this paper, the dual-gate structure＇s effects of reducing the off-state leakage current while seldom lowering the on-state current is predicted by theoretical analysis comparing with the single gate a-Si TFT. The SPICE simulation results prove that dual-gate structure can reduce about half of the leakage current. In order to evaluate the effect of response time reduction, this paper establishes a compact model of the response time t and leakage current Ioff. According to the Matlab simulation, one can find the response time is shorted from 380 ms to 320 ms when the leakage current is 20 pA, and from 530 ms to 360 ms when the leakage current is 35 pA, indicating a rising in frame rate from 2 Hz to 3 Hz. At last, basing on the t-Ioff model, this paper points out that reducing the radius of electrophoretic particle or using a larger storage capacitor are also crucial for EPD＇s response time optimization.

关 键 词：电泳显示器 不定形硅双栅薄膜晶体管 漏电流 响应时间 SPICE模拟 

分 类 号：TN27[电子电信—物理电子学]