一种功耗优化的均衡器结构设计  

A Power Optimized Equalizer Structure Design

作　　者：齐悦[1] 李涵[1] 辛茹[1] 王沁[1] 

机构地区：[1]北京科技大学信息工程学院,北京100083

出　　处：《微计算机信息》2007年第35期266-267,299,共3页Control & Automation

基　　金：国家自然科学基金(50674010)

摘　　要：本文提出了一种可动态开关运算器件的均衡器结构,使得在硬件实现时可以降低功耗。根据实际的信道环境通常都是变化的特点,在不同情况下动态改变均衡器中滤波器抽头的个数,在信道较好时将对结果几乎没有影响的抽头之乘法运算关掉,使得均衡器在以更少的抽头数目工作,以此达到降低功耗的目的。以DVB-C规定的多径信道为例,仿真结果显示,在保持性能不变时最多可减少15%以上的乘法运算。SNR损失0.2dB时最多可以关掉75%的乘法运算。在实际应用中可根据具体性能要求设计,该方法可灵活应用到类似设计中。This paper presents a low-power equalization structure which can dynamic switch on/off the multiply-accumulation to reduce the power when realized in hardware. There are different channel conditions in a communication system. The equalizer is generally designed for the worst case but not for the typical or best case： According to the fact that channel situation is variational, power reduction can be achieved by the adaptive changing tap＇s length. Powering down the tap＇s multiplication where the tap is no contri- bution to the result, Take the Multi-path channel based on DVB-C as example, the simulation shows that 15% multiplication reduction can be achieved without losing performance. And with 0.2dB SNR decreasing the taps of filter block can be powered down more than 75% in average. This method can be extended to similar design easily.

关 键 词：低功耗 均衡器 体系结构 集成电路 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]