基于CMOS工艺的低噪声高稳定性LDO的设计  

Design of Low Noise High Stability LDO Based on CMOS Process

作　　者：徐静萍[1] 来新泉[2] 

机构地区：[1]西安邮电学院电信系,西安710121 [2]西安电子科技大学电路CAD研究所,西安710071

出　　处：《半导体技术》2007年第12期1056-1059,共4页Semiconductor Technology

基　　金：国家教育部博士点基金资助项目(20010701003)

摘　　要：介绍了一种LDO线性稳压器电路,给出了基本结构及其工作原理。重点分析了产生噪声的原因以及用旁路滤噪电路实现低噪声、用内部动态补偿电路实现高稳定性的电路结构和性能特点,针对输出短路或者负载电流过大设计了过流保护电路。整个电路采用HYNIX 0.5μmCMOS工艺实现,基于HSPICE进行仿真验证,输出噪声为1μV(rms),典型环路增益为60 dB,相位裕度65°,证明了稳压器的低噪声和高稳定性。LDO （ low dropout） linear regulator was introduced, the basic structure principal were presented. The sources of the noise were analyzed emphatically, the bypass and operational capacitor filter circuit and dynamic frequency compensation circuit were adopted in order to achieve low noise and high stability. Over current protecting circuit was added to deal with shorted output or too large load current. Based on HYNIX 0.5 μm CMOS process, HSPICE simulation results show that output noise is 1 μrms, loop gain is 60 dB and phase margin is 65°, it proves the low noise and high stability of LDO.

关 键 词：LDO线性稳压器 旁路滤噪 低噪声 动态补偿 

分 类 号：TN402[电子电信—微电子学与固体电子学]