片上系统中外部存储控制器的设计与优化  

The Design and Optimization of External Memory Controller In SoC

作　　者：罗欣武[1] 戎蒙恬[1] 刘文江[1] 

机构地区：[1]上海交通大学电子工程系,上海200240

出　　处：《上海交通大学学报》2007年第6期929-933,共5页Journal of Shanghai Jiaotong University

基　　金：上海应用材料研究与发展基金资助项目(0501)

摘　　要：针对片上系统（System on Chip,SoC）中多主设备、多猝发操作的访问特点,提出并实现了一种新的片内总线访问外部存储器的结构,并对核心模块的设计与优化进行了分析.该结构通过分割传输方式使内部总线平均利用率提高了29%~34%;并且,通过对SDRAM控制模式的动态切换有效地降低了外存读写延迟和功耗.An advanced mechanism for off-chip memory access in SoC adapted to the multi-master and burst-oriented transfers was presented, and some details about the key modules and optimization were discussed. Through split transactions the new structure improves the efficiency of on-chip bus by average of 29% to 34%. On the other hand, less memory access latency and power consumption can be gained using a dynamic SDRAM control mode.

关 键 词：外存控制器 片内总线 分割传输 

分 类 号：TN47[电子电信—微电子学与固体电子学]