利用UML-RT序列图支持基于事务的SoC系统级功能验证  

Using the UML-RT Sequence Diagrams for Transaction-Based System-on-Chip System-Level Verification

作　　者：余金山[1] 谭庆平[1] 李暾[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2007年第3期100-104,共5页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(60403048)

摘　　要：SoC基于事务的验证方法面临的一个重要问题是如何设计验证系统级复杂交互行为的事务测试序列。基于场景的序列图是设计人员捕获系统级功能规约的良好方法。本文提出了一种利用UML-RT序列图捕获SoC各个IP核之间的通信协作行为,为基于事务的验证建立高层规约,指导系统级测试序列生成的方法。我们自行开发了一个基于构件的事务验证环境SoC-CBTVE,并在该环境中利用本文的方法对一个典型的SoC设计进行了验证和分析。实验结果表明,利用UML-RT序列图能够捕获SoC系统级IP核之间的复杂通信行为,有效支持SoC系统级功能验证。An important problem faced by transaction-based systemon-chip verification is how to design the complex transaction test sequence.Scenario-based sequence diagram is a good way to capture the system-level functional specification.In the paper,we propose a method to support the transaction-level verification of SoC based on the UML-RT sequence diagrams.We use the UML-RT sequence diagram to capture the communication and collaboration behaviours among IP cores in SoC and build a high-level specification for transaction-level verification.Then these sequence diagrams will be used to guide the generation of transaction test sequences.We develop a component-based transaction verification environment named SoC-CBTVE.In SoC-CBTVE,using the method,we verify a typical SoC design.Experimental results show that the UML-RT sequence diagram can capture the complex communication behaviours among IP cores in SoC design,and efficiently supports the SoC system-level functional verification.

关 键 词：UML-RT序列图 系统芯片 事务 验证 

分 类 号：TP311.5[自动化与计算机技术—计算机软件与理论]