B3G系统吉比特互联通道设计与实现  

Design and Implementation of Gigabit Interlink Channel for B3G Communication System

作　　者：刘红亮[1] 周宗仪[1] 朱光喜[1] 谭力[1] 

机构地区：[1]华中科技大学,湖北武汉430074

出　　处：《无线电通信技术》2007年第6期49-51,共3页Radio Communications Technology

基　　金：国家"863"基金资助项目(2003AA12331005)

摘　　要：B3G移动通信系统中,如何为系统中诸多的处理、控制单元提供一种高效、高带宽的互联通道,成为系统设计中极具挑战性的研究点。提出了一种改进的串行吉比特互联构架与实现方案,并在设计中引入缓冲池解决了通道失效引发的丢帧问题,以先进的通信计算机构架ATCA为平台,应用Xilinx公司FPGA内嵌的RocketIO实现了B3G单元高速互联。系统测试表明,各单元互联通道速率达2Gbps,误码率低于10-12。How to provide a kind of interlink channel with high effficiency,broad bandwidth becomes a challenging issue in B3G mobile system. An improved design architecture of the gigabit serial interlink is proposed in this paper , and the buffer pool is employed in the design to resolve frame lost during channel invalidation, based on advanced telecom computing architecture platform , both of which have been realized with the RocketIO embedded in Xilinx＇s FPGA and applied to B3G interlink. The system test result shows that channel data rate is up to 2Gbps,and the bit error rate （BER） is lower than 10^-12.

关 键 词：吉比特 B3G Rocket10 通信计算机架构 

分 类 号：TN92[电子电信—通信与信息系统]