K变模可拟计数器竞争冒险现象的消除  

Clearance of Race and Hazard for Changeable Modulo-K Reversible Counter

作　　者：李莉[1] 

机构地区：[1]北京电子科技学院,北京100070

出　　处：《现代电子技术》2007年第24期185-186,190,共3页Modern Electronics Technique

摘　　要：竞争冒险作为数字电路设计中经常会遇到的现象,存在可能导致高速电路或毛刺敏感电路的逻辑错误。以k变模可逆计数器设计中出现的竞争冒险现象为例,从程序、仿真波形、综合电路等方面较为详细地介绍了应用VHDL进行数字电路设计中竞争冒险现象产生的原因,并提出了采用同步时序电路设计的原则消除竞争冒险的方法。Race and hazard often occur in digital circuit design, which always effect circuit logic function for high speed circuit or race sensitive circuit. This article takes changeable Modulo- k Reversible Counter as an example, analyzes the reason of race and hazard occured in digital circuit design with VHDL language from many guises, such as the design of program, simulation wave and synthesis circuit, and gives the asynchronous sequential logic design method for clearance race and hazard.

关 键 词：竞争冒险 计数器 VHDI 同步时序电路 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]