基于NUMA MPSoC的FFT并行化算法设计及实现  

Parallel Solution of FFT on FPGA-Based NUMA Multiprocessor System on Chip

作　　者：张冰[1] 杜高明[2] 李丽[1] 杨盛光[1] 

机构地区：[1]南京大学微电子设计研究所,江苏南京210093 [2]合肥工业大学微电子设计研究所,安徽合肥230009

出　　处：《微电子学与计算机》2007年第12期109-112,共4页Microelectronics & Computer

摘　　要：如何充分利用多个处理器任务级并行或线程级并行的特点提高性能已成为MPSoC设计的关键问题之一。在建立基于非均匀存储型(Non-Uniform Memory Access Architecture,NUMA)MPSoC平台的基础上,以快速傅里叶变换为例,遵循减少核间通讯及平均分配工作负载的原则,提出其并行化方法,设计出相应的并行程序及底层驱动,在FPGA原型芯片的运行环境下分析系统性能。试验结果表明,在4核MPSoC的FPGA原型系统中最高加速比可达2.65,具有较好的并行执行效率。Recent advances in VLSI transistor capacity have made it possible to integrate a larger number of computation resources on a single chip. Scheduling of multi-task applications on computational units is key to meeting performance constraints and power budgets. We present here the design and implementation of a FPGA-based NonUniform Memroy Acess（NUMA） multi-processor system on chip. A parallel algorithm for FFT is mapped to our multi-proccessor system as an exafmple. The results prove that our FPGA-based 4-core platform is efficient for the parallel FFT algorithm.

关 键 词：NUMA 多核片上系统 FFT 并行算法 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]