基于HDL的PAL制数字视频图像采集控制器设计  

The Controller Design of Digital Video Data Acquisition of PAL Based on HDL

作　　者：钱敏[1] 李富华[1] 黄秋萍[1] 李文石[1] 刘蓓[1] 

机构地区：[1]苏州大学微电子系,江苏苏州215021

出　　处：《微电子学与计算机》2007年第12期191-194,共4页Microelectronics & Computer

基　　金：苏州市科技招标项目

摘　　要：介绍了PAL制电视信号的组成和数字视频图像采集的过程;用Verilog-HDL设计了PAL制数字视频图像采集的控制电路;该控制器为DSP进行实时数字图像处理准备好RGB数据,其中包括数据采集控制电路、存储器接口、总线切换电路和DSP接口等电路;在ModelSimPLUS6.0SE软件中进行了仿真和调试,结果表明实现了PAL制数字视频图像采集的相关功能。The composition of PAL TV signal and the procedure of digital video image acquisition processing are simply introduced. The controller of digital video image acquisition is designed with VedlogHDL, which prepares the RGB data for the DSP＇s real time image process. The total circuit includes data acquisition circuit, memory interface, bus switch- ing circuit and DSP interface. The design is simulated in ModelSim PLUS 6.0SE tool and tested. The result indicates that the digital video image acquisition function of PAL is realized.

关 键 词：PAk视频信号采集 控制器 VERILOGHDL 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN915