基于CMOS工艺流水线型模数转换器采样保持电路设计  

CMOS-based Design of S/H Circuit of Pipelined A/D Converter

作　　者：季红兵[1] 

机构地区：[1]南通大学,江苏南通226019

出　　处：《南通大学学报（自然科学版）》2007年第4期71-74,共4页Journal of Nantong University(Natural Science Edition)　

基　　金：南通市工业科技创新计划资助项目(A4036)

摘　　要：采样保持电路作为流水线模数转换器中的重要单元一直是高速高分辨率模数转换器研究设计者十分关注的内容.文章介绍了基于CMOS 0.6μm工艺的流水线模数转换器前端采样保持电路以及运放电路的设计仿真.该电路采用电容下极板采样、折叠式共源共栅技术,有效地消除了开关管的电荷注入效应、时钟馈通效应引起的采样信号的误差,提高了采样电路的线性度,节省了芯片面积,降低了功耗.A sample-and-hold （S/H） circuit as the key part of the analog-to-digital（A/D） converter always attracts the researcher and designer of A/D converter. This paper introduces the design and simulation of the S/H and OTA circuit based on CMOS 0.6um technique. The sample and hold circuit is employed by the capacitance bottom plate sampling technique, which can eliminate the charge injection error of switch MOSFET. The bootstrapped switch is used to improve the linearity of the switch, therefore to improve the linearity of the sampIe/hold circuit. In order to accelerate the amplifier＇s speed, save the chip area and eliminate the clock feed-through effect, a differential folded Cascode common source common gate op amp is designed.

关 键 词：流水线 模数转换器 采样保持 

分 类 号：TN45[电子电信—微电子学与固体电子学]