基于分布式算法的高速高FIR滤波器实现  

Design of High Speed and High FIR Digital Filters Based on Distributed Algorithm

作　　者：邵婷[1] 刘国华[1] 赵军朝[1] 

机构地区：[1]西北机电工程研究所,陕西咸阳712099

出　　处：《火炮发射与控制学报》2007年第4期23-26,共4页Journal of Gun Launch & Control

摘　　要：为处理高速实时信号,利用分布式算法对FIR滤波器的硬件实现进行了探讨。在数乘累加运算的理论上,对分布式算法的串行、并行和串并结合的FPGA硬件实现方法进行了研究。结合FPGA查找表结构,兼顾资源及运行速度的要求,用串并结合的方法设计了16阶常系数FIR滤波器,并在Quartus II4.1下进行仿真,仿真结果证明了该算法的有效性和实时性。该方法较用乘法器实现的直接FIR滤波有处理速度快,占有资源小的优点,在处理实时信号方面有较大的实用价值。In order to deal with high discussed. By means of Distributed speed and real time signal, hardware design of FIR digital filter was Algorithm （DA）, based on theory of data accumulation algorithm, FPGA hardware design method of parallel DA, series DA, and series-parallel DA were studied. By use of speed, resource and series-parallel DA, 16-step constant coefficients high speed FIR digital filter was designed, and the filter was simulated under the conditions of Quartus Ⅱ 4.1. Simulation result showed that the design method has validity, real time effectiveness and feasibility. Compared with the directed FIR filter design method using multipliers, this method has higher speed and lower cost, and greater practical value in dealing with real time signal.

关 键 词：信息处理技术 FPGA 分布式算法 FIR滤波器 

分 类 号：TN713.7[电子电信—电路与系统]