12位100MSPS CMOS双采样/保持电路  

A 12-Bit 100-MSPS CMOS Double Sample/Hold Circuit

作　　者：陈达[1] 于奇[1] 吴霜毅[1] 宁宁[1] 伍翠萍[1] 王浩娟[1] 

机构地区：[1]电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2007年第6期848-851,856,共5页Microelectronics

基　　金：Intel Research Council基金资助项目(2006070)

摘　　要：提出了一种基于时间交织原理的双采样/保持电路;分析了其相比于传统单采样技术实现高速度、高精度,同时降低功耗的优点。设计的栅压自举开关有效提高了采样的线性度。另外,为满足双采样技术的特殊应用,设计了带双边型开关电容共模反馈的全差分运放。采用SMIC0.18μmCMOS工艺仿真设计的双采样/保持电路可实现12位采样精度、100 MSPS采样速率、92.34 dB线性度和29 mW功耗的高性能。A double sample/hold （DSH） circuit was proposed based on time-interleaving theory. Comparedto ／conventional single sample/hold （SSH） circuit, the proposed DSH has the advantage of achieving high speed and high resolution with low power dissipation. The linearity of sampling was effectively improved by using boot- strapped switch. For specific application of the DSH, a fully-differential operational amplifier with double switched- capacitor common-mode feedback （DSC-CMFB） circuit was designed. Simulation based on SMIC＇s 0. 18 t^m CMOS technology showed that the DSH circuit had 12-bit resolution up to Nyquist frequency at sampling rate of 100 MSPS with 92. 34 dB spurious free dynamic range at 29 mW power dissipation.

关 键 词：双采样/保持电路 栅压自举开关 双边型开关电容 共模反馈 

分 类 号：TN792[电子电信—电路与系统]