一种40 MSPS 10位流水折叠分级式A/D转换器  

40 MSPS 10-b Pipelined Folding and Subranging A/D Converter

作　　者：孟晓胜[1] 王百鸣[2] 

机构地区：[1]深圳大学光电子学研究所 [2]深圳大学信息工程学院EDA技术中心,广东深圳518060

出　　处：《微电子学》2007年第6期874-877,共4页Microelectronics

基　　金：国家自然科学基金重大研究计划资助项目(90407001);深圳市科技计划资助项目(200512)

摘　　要：探讨和研究基于流水线(Pipelined)技术的折叠分级式A/D转换器(ADC),理论分析了它的原理和一般结构,给出了一个具体结构的ADC框图和具体的折叠电路,并得出了实际制作的ADC的测试图。该折叠分级式ADC的输入频率可达到1 MHz,2级折叠电路产生的高2位加上子ADC产生的8位,使A/D转换器可达到10位的分辨率,采样率最大为40 MSPS。Researches were made on pipelined folding and subranging A/D converter （ADC）. The principle and general structure of the AI）C were analyzed. A detailed block diagram of a specific AI）C and a detailed folding circuit were presented, as well as test results of the actual AI）C. By cascading 2-b folding circuits with 8-b sub ADC, the folding and subranging AI）C has an input frequency of 1 MHz, a sampling rate of 40 MSPS and 10-bit resolution.

关 键 词：A/D转换器 折叠 流水 分级 模拟余差信号 绝对值电路 

分 类 号：TN792[电子电信—电路与系统]